Description
The role leads a complex ASIC subsystem for Google's Edge-AI and data center infrastructure, defining high-performance hardware/software interfaces, micro-architecture, block partitioning, and design flows. The position collaborates with software, verification, and physical design teams and requires a bachelor's degree in Electrical Engineering or equivalent practical experience, eight years of RTL development using Verilog, and experience with speed interfaces, micro-architecture, verification, logic synthesis, and timing closure. Preferred qualifications include scripting, processor and memory architecture, low-power design, FPGA and SoC knowledge, and formal verification. The role is based in Tel Aviv or Haifa, Israel, and requires in-person interviews.
