Description
NVIDIA is seeking an ASIC Top Floorplan Design Engineer to develop, craft, and optimize floorplans during early SoC and GPU development. The role collaborates with architects, design leads, physical design leads, and package leads; drives area reviews; addresses timing and routing congestion; and builds or improves AI-enabled tools and infrastructure. Candidates need a master’s degree in electrical engineering, computer science, or computer engineering, at least one year of equivalent work or learning experience, and experience with Verilog or System Verilog, physical design, floorplanning, power and clock distribution, packaging, P&R, timing closure, and programming in Python, Perl, or C/C++.
