Summary from listing
The ASIC Top-Level Verification Engineer will develop SoC-level testcases, prepare and maintain hardware-emulation platforms, define verification strategies, create C-based software-driven tests, debug RTL and failing tests across SystemC/TLM, hardware emulation, and silicon, and contribute to CI regression flows. The role may involve UVM VIPs, gate-level simulation, formal connectivity verification, ASIC compilation for emulators, and scripting. Candidates should have ASIC top-level verification experience, with SystemVerilog/UVM, AMBA, ARM, JTAG, external interfaces, memory interfaces, or clock-and-reset verification experience preferred.
