Description
Hewlett Packard Enterprise is hiring an ASIC Verification Engineer for its networking silicon development team in Sunnyvale, California. The role owns block-level or subsystem verification from test planning through coverage closure, develops UVM environments, performs random testing and functional coverage analysis, debugs complex SoC designs, and collaborates with cross-functional teams. Candidates need at least five years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with simulation tools such as Cadence Xcelium, Synopsys VCS, and Mentor Questa. The position is hybrid, with an expectation of being in the office two days per week, and offers a base salary of USD 120,000–243,000 in California.
