Description
Hewlett Packard Enterprise is hiring an ASIC Verification Engineer to develop and enhance ASIC verification environments using SystemVerilog, UVM, and constrained-random techniques. The role involves building block-level, subsystem, and full-chip verification environments, executing simulation test suites, driving tape-out readiness through coverage and gate-level analysis, debugging with logic designers and software teams, and developing Perl, Python, and/or Shell automation scripts. The position is onsite at an HPE office and requires a BSEE or MSEE degree and at least five years of ASIC verification experience.
