Description
NVIDIA’s Clocks team is hiring an experienced ASIC Design Verification Engineer to validate clocking and reset logic in Tegra and GPU products. The role owns test plans, automation, verification flows, coverage metrics, test execution, bug fixing, and productization, while collaborating with architecture and design teams and coordinating across time zones. Candidates need a BS or MS in EE/ECE or equivalent experience, at least three years of design verification experience, strong System Verilog, UVM, C++, and scripting skills, and prior pre-silicon test-plan experience. The posting is marked hybrid and lists base salary ranges of 116,000–189,750 USD for Level 2 and 136,000–218,500 USD for Level 3, with equity and benefits.
