Summary from listing
Ericsson Silicon is hiring a Design Verification Engineer - ASIC IP in Austin, Texas, for an on-site hybrid schedule. The role leads block-level and top-level ASIC and IP verification, develops RTL testbenches, uses SystemVerilog and UVM, creates TLM behavioral models, participates in hardware emulation and acceleration verification, drives software-driven verification, and mentors team members. Candidates need 10+ years of RTL debugging experience, IP/ASIC/SoC/FPGA verification experience, SystemVerilog/UVM proficiency, knowledge of at least one technology domain, scripting skills, and a BS or MS in a relevant field. The position offers medical and dental benefits, a 401(k) match, paid leave, and other company benefits.
