ASIC Verification Engineer, Staff Level at Synopsys

Location: Bengaluru, Karnataka
Level: senior
Posted: Sep 22, 2026

Description

Synopsys is hiring a DesignWare IP Verification Engineer to verify IP blocks and subsystems across DesignWare product lines. The role involves developing UVM-based verification environments, test plans, checkers, assertions, and functional coverage; debugging complex functional failures across protocols such as Ethernet, USB, and PCI Express; analyzing regression results; and building Python or shell automation tools. The engineer will collaborate with design, firmware, quality, and architecture teams and contribute to signoff quality, coverage closure, and verification productivity.

Required Skills

SystemVerilog
UVM
VCS
Python
Waveform analysis
Coverage analysis

Additional Information

Minimum Education: Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering; MS with 3+ years of experience is also acceptable.
Required Previous Experiences: 5+ years of hands-on IP or SoC verification experience, or 3+ years with an MS.
Real project experience developing verification environments, test plans, checkers, assertions, and functional coverage.
Hands-on experience with VCS and associated debug tools.
Experience debugging complex functional failures, analyzing regression results, tracking issues to closure, and supporting verification signoff.
Experience writing Python, Perl, or shell scripts or automation utilities.
Preferred Qualifications: Experience with DesignWare IP or similar synthesizable IP verification projects.
Familiarity with Ethernet, USB, or PCI Express protocols.
Exposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure.