Description
Synopsys is hiring an experienced ASIC Digital Verification Engineer to design and execute verification environments and testbenches for Interface IP protocols, including DDR, PCIe, CXL, and Ethernet. The role focuses on SystemVerilog and UVM, functional coverage, bug fixing, and mentoring junior engineers, with a specific contribution to the architecture and execution of a DDR controller digital core product. The posting emphasizes extensive ASIC verification experience, simulation-tool proficiency, strong analytical and communication skills, and the ability to lead junior engineers.
