Description
Synopsys is hiring an ASIC Verification Staff Engineer to design, implement, debug, and validate System Verilog-based verification environments for DesignWare IP cores. The role covers test planning, functional coverage, regression testing, protocol validation, verification automation, methodology development, and collaboration with RTL designers and global verification teams. Candidates need a BSEE with 5+ years or MSEE with 3+ years of relevant ASIC or IP verification experience, along with expertise in UVM/OVM/VMM, simulation tools, scripting, and protocols such as MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB.
