Associate Design Verification Engineer at Analog Devices, Inc.

Analog Devices is hiring an Associate Design Verification Engineer to develop test benches and perform design verification of new digital, analog, and mixed-signal products before tape-out. The entry-level role involves creating SystemVerilog/UVM test environments, conducting code coverage analysis, debugging simulation failures, supporting verification planning and documentation, collaborating with design teams, and identifying design issues under senior guidance. The position requires basic proficiency in SystemVerilog and UVM, scripting knowledge, Verilog RTL understanding, familiarity with digital interfaces and simulation tools, and offers 0–2 years of relevant experience or new graduates.