Description
Silicon Labs is hiring an Associate Staff Design Engineer to lead and execute the end-to-end backend physical design flow for complex SoCs and ASICs, including synthesis, constraints, STA, logical equivalence, UPF and low-power checks, timing sign-off, ECOs, PPA optimization, and GDSII delivery. The role requires 9–10 years of ASIC physical design experience, a bachelor’s or master’s degree in ECE, EEE, VLSI, or a related field, and hands-on expertise with industry-standard EDA tools. The position is hybrid and located above Tai Seng MRT station.
