CAD Engineer – Design Verification Methodology at Apple

Department: Hardware

Language

Location: Chorrillos, Department of Lima · San Francisco, California · +2
Level: senior
Posted: Apr 15, 2026

Description

The role develops, maintains, and enhances software systems for regression-testing Apple silicon designs in software simulation, identifies and reports defects, and supports chip design engineering. The position works with EDA vendors, debugs vendor-tool problems, and guides engineers through complex issues. It requires a bachelor’s degree, 10 years of relevant experience, RTL regression-system experience, Python programming, and strong problem-diagnosis and communication skills.

Required Skills

Python
RTL regression
Tool debugging
Verilog
SystemVerilog
VCS
ModelSim
Cadence
Synopsys

Additional Information

Minimum Education: Bachelor’s degree
Required Previous Experiences: 10 years of relevant experience
Developing, maintaining, and enhancing an existing RTL regression system
Debugging vendor tool problems
Preferred Qualifications: TCL or Perl experience
Artificial intelligence and machine learning experience
DV team collaboration
Implementing new functionality or optimizing existing methods
MSEE, CE, or CS degree
Verilog, SystemVerilog, and VHDL knowledge
VCS, XCelium, or ModelSim experience
Cadence or Synopsys emulation experience
Communication skills and customer support experience
Verdi or Indago familiarity
C and C++ knowledge

About Apple

Apple

technology industryCupertino, CA

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