Description
Apple is hiring a Physical Design Verification Engineer to architect, develop, maintain, and improve physical design verification flows for silicon technologies. The role involves creating and modifying DRC, LVS, ERC, and MFILL runsets, supporting place-and-route and physical implementation flows, collaborating with design and chip integration teams, and working with tool vendors and foundries on PDK performance. The minimum qualification is a bachelor's degree plus eight years of relevant industry experience, with Calibre/ICV runset coding, Perl, Python, Tcl, Shell, Makefile, and C++ knowledge required or preferred.
