CAD Engineer - Timing for Gate-Level Flows & Methodologies at Apple

The STA CAD Engineer will join Apple’s Silicon Technologies group to improve the performance of Apple Silicon by developing and maintaining gate-level static timing analysis flows, debugging constraints and timing-closure issues, supporting timing and power-reduction automation, and collaborating with design teams and EDA vendors. The role requires a bachelor’s degree and at least 10 years of relevant industry experience, with expertise in static timing tools, Python or Tcl, CAD-flow development, large SoC designs, and timing models preferred.