CAD Engineer - Timing for Gate-Level Flows & Methodologies at Apple

The STA CAD Engineer will join Apple’s Silicon Technologies group to improve the performance of Apple Silicon through static timing analysis and closure. The role develops and maintains gate-level STA flows, debugs constraints and timing issues, supports timing and power-reduction methodologies, works with EDA vendors, and contributes to post-silicon timing debugging. A bachelor’s degree and three years of relevant industry experience are required; experience with STA tools, Python or Tcl, large SoC designs, and timing fundamentals is preferred.