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Chip Design Engineer at Ricursive Intelligence

Department: Engineering

Setup
On-site
Location
Palo Alto, California
Type
Full-time
Level
senior
Posted

Description

Ricursive Intelligence is hiring a Physical Design Engineer to own the full chip design flow from synthesis through tapeout, including DFT insertion, floorplanning, PDN, placement, CTS, routing, timing, power, EM/IR, and physical signoff. The role focuses on closing complex, PPA-critical blocks in advanced nodes, supporting chip-design infrastructure and automation, and driving design improvement strategies. Candidates need a relevant bachelor's degree, at least five years of hands-on physical-design experience, production-stack fluency, strong Tcl and Python scripting, and a successful tapeout record.

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