Description
Astera Labs is expanding its operations by establishing a strategic R&D center in Israel to develop complex semiconductor chips aimed at addressing critical 'data bottlenecks' essential for large-scale AI. They are looking for a highly skilled Chip Top Physical Design Engineer who will play a crucial role in implementing the physical design of the SoC Top level for chips used in global AI clusters. This engineer will be responsible for driving full-chip convergence, performing top-level physical implementation, resolving complex signal integrity issues, and collaborating with various internal teams to optimize Power, Performance, and Area (PPA) targets.
