Cloud Hardware Development Engineer at ADCI - Karnataka

Department: aws

Compensation

$159,200 – $247,600/yr

Setup: On-site
Location: Austin, Texas · Seattle, Washington · +1
Type: Full-time
Level: senior
Posted: Sep 9, 2026

Description

AWS is hiring a Cloud Hardware Development Engineer to define GPU-accelerated server architectures for AI/ML training and inference, translate them into component specifications, and lead validation from PCBA bring-up through rack integration. The role owns hardware debugging, ODM/JDM development, fleet quality metrics, root-cause analysis, and continuous improvement across thermal, mechanical, power, signal integrity, PCIe, memory, and accelerator subsystems. Candidates need a bachelor's degree in electrical or computer engineering, at least seven years of server or large-scale infrastructure hardware development experience, and experience with server technologies and full product lifecycles. The position is based in Seattle, Austin, or Cupertino, with annual base salaries ranging from $159,200 to $247,600 USD depending on location.

Required Skills

Server architecture
Signal integrity
Power delivery
PCBA bring-up
Root cause analysis
Fleet quality
ODM partners

Additional Information

Minimum Education: Bachelor's degree in electrical engineering, computer engineering, or equivalent
Required Previous Experiences: 7+ years of hardware design and development experience for server, compute, or large-scale infrastructure platforms
Experience with server technologies including thermal/mechanical design, power delivery, high-speed signal integrity, or accelerator subsystems
Experience leading hardware development through the full product lifecycle from concept through production ramp
Preferred Qualifications: Master's degree or above in electrical engineering, computer engineering, or equivalent
Experience working in data centers or critical infrastructure
5+ years of experience working with ODMs through the product development and manufacturing lifecycle
In-depth expertise in high-speed bus design, signal integrity analysis, or power delivery for GPU/accelerator platforms
5+ years of experience with hardware bring-up, debug, and root cause analysis across PCIe, NVMe, memory, and accelerator interconnects
Experience owning fleet quality metrics and driving design improvements based on operational failure data
Experience with thermal/mechanical design for high-power-density compute platforms
Track record of defining engineering standards and design best practices adopted across teams or partner organizations