Co-design engineer for future computing architectures in HPC - M/F at ADSN Career

CEA List is hiring a Co-design Engineer for future computing architectures in HPC on a 24-month fixed-term contract at the Nano-Innov site in Saclay, France. The role develops HW/SW co-design methodologies and tools for high-performance computing and AI systems, using VPSim, A-DECA, QEMU-based emulation, and Python. Responsibilities include modeling optical/photonic interconnect architectures, exploring chiplet designs, optimizing power, performance, area, and sustainability, collaborating with research partners, contributing to open-source software, and disseminating research results. Candidates need an engineering, master's, or PhD degree in a relevant field and knowledge of hardware description languages, digital architectures, high-level and scripting languages, development tools, and Git.