Description
Synopsys is hiring an Application Engineer focused on ASIC timing constraints and SDC verification. The role partners with semiconductor customers in the Bengaluru region to solve constraint-flow challenges, deploy and optimize Synopsys constraint tools, debug timing and clock issues, develop constraint methodologies, automate workflows, and support customer adoption. Candidates need a degree in electronics, computer science, or microelectronics, at least five years of ASIC design or verification experience, end-to-end SDC and constraint-flow expertise, knowledge of RTL and timing closure, and advanced scripting skills.
