CPU Architect / RTL Design Engineer for MIPS CPU Subsystem at Baidu USA

Location: Sunnyvale, California
Type: Full-time
Level: mid
Posted: Apr 28, 2026

Description

This role is for designing a cost-effective, high-performance, low-power, small-area controller for a cellular modem, with responsibilities spanning CPU development and design integration for a MIPS CPU subsystem. The engineer will conduct fundamental research on new CPU architecture directions, analyze workloads to identify performance bottlenecks, and translate architecture and micro-architecture ideas into design and modeling work that ultimately reaches silicon in collaboration with multi-national teams and leading-edge process technology.

Required Skills

CPU design
CPU architecture
Performance analysis
Data-driven analysis
RTL integration
Microarchitecture
RISC architecture

Additional Information

Minimum Education: Master's degree in Electrical Engineering, Computer Science, or Computer Engineering
Required Previous Experiences: At least 5 years of CPU-related architecture, RTL, verification, or implementation design experience
Preferred Qualifications: PhD in Electrical Engineering, Computer Science, or Computer Engineering
8+ years of CPU-related architecture, RTL, verification, or implementation design experience
Familiarity with SMP and snoop-based multiprocessor architecture
Familiarity with synthesis, power analysis, and post-silicon debugging
Cross-site working experience
Knowledge of modeling, DV, and OS
Experience with foundry, post-silicon, FPGA, DVT, and SLT debug