CPU Cache Microarchitect/RTL Engineer at Apple

Department: Hardware

Location: Beaverton, Oregon · California · +1
Level: senior
Posted: Apr 13, 2026

Description

Apple’s Silicon Engineering Group is hiring a CPU Cache Microarchitect/RTL Engineer to develop and verify CPU cache subsystem architecture and RTL designs for multi-processor systems. The role covers micro-architecture specification, RTL ownership, verification, performance exploration, and physical design delivery, with a minimum of a bachelor’s degree and 10+ years of relevant industry experience.

Required Skills

Microprocessor architecture
RTL design
Verilog or VHDL
Waveform debugging
Coherence protocols
C or C++

Additional Information

Minimum Education: Bachelor’s degree
Required Previous Experiences: 10+ years of relevant industry experience
Microprocessor architecture experience
Logic design with timing and power implications
Verilog or VHDL experience
Simulator and waveform debugging experience
Preferred Qualifications: Coherence protocols and interconnects
High-performance low-latency, high-bandwidth design
Memory subsystem queuing and scheduling
SRAM design basics
Multi-clock and power-domain management
Prefetchers and replacement policies
DFT and error detection and correction
Low-power microarchitecture
High-performance CPU microarchitecture trade-offs
C or C++ programming
Perl or Python

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