Description
The CPU CDC/RDC/STA Engineer will analyze CPU designs, develop and maintain Clock-Domain Crossing, Reset-Domain Crossing, and Static Timing Analysis constraints and sign-offs, and drive fixes across multiple design sites. The role collaborates with RTL, design verification, CAD, physical design, and EDA vendor teams, recommends System Verilog assertions, debugs vendor tools, and improves CDC/RDC/STA methodologies. Minimum qualifications include a bachelor's degree, at least 10 years of relevant industry experience, CDC/RDC experience, Synopsys or Real Intent tool experience, TCL or Perl scripting, and Verilog experience.
