Description
The CPU CDC/STA Engineer will analyze CPU designs, develop and maintain CDC, RDC, and STA constraints and methodologies, and drive sign-offs across multiple design sites. The role collaborates with RTL, design verification, CAD, physical design, and EDA vendor teams, recommends System Verilog assertions, debugs vendor tools, and improves verification methodologies. A minimum bachelor's degree and scripting experience with TCL or Perl are required; experience with STA, CDC, RDC, System Verilog Assertions, Design Verification, Verilog, and tools such as Spyglass, VC-Static, PrimeTime, or Meridian is preferred.
