Description
Intel is hiring an experienced memory and datapath design methodology engineer for its ACE India P-Core design team in Bengaluru. The role leads design analysis and methodology enablement for SRAM, register file, and ROM memory blocks and datapath subsystems targeting CPU designs above 5 GHz with low power and optimized area. Responsibilities include static timing analysis, collaboration with layout and floorplanning teams, back-end feature implementation, memory post-silicon analysis, and statistical variation analysis. The position requires a master's degree with at least 8 years of related experience or a bachelor's degree with at least 10 years, with preferred expertise in synthesis, place-and-route tools, Verilog, scripting, and SPICE.
