Description
The Soft CPU Design Engineer will join Altera’s IP Engineering team in San Jose, California, designing and implementing high-performance Soft CPU cores optimized for FPGA architectures. The role covers micro-architecture, RTL design, PPA optimization, FPGA synthesis and timing closure, configurable instruction-set extensions, and hardware validation. Candidates need a bachelor’s, master’s, or Ph.D. in a relevant technical discipline, at least three years of digital design experience focused on CPU/processor RTL and FPGA implementation, and advanced SystemVerilog or Verilog proficiency. The regular position pays $133,200 to $192,800 USD in the Bay Area, with incentive opportunities.
