CPU Design Timing Engineer at Apple

Department: Hardware

Compensation · Listed in posting

$150,400 – $277,600

Location: California
Level: mid
Posted: Apr 14, 2026

Description

The CPU Design Timing Engineer is responsible for CPU timing closure, including developing and scripting timing flows, working with CAD, CPU micro-architects, and implementation engineers, and performing timing analysis and closure. The role requires a bachelor's degree and at least three years of relevant experience, along with static timing analysis, noise analysis, variation modeling, TCL, and Perl or Python skills.

Required Skills

Static timing analysis
Noise analysis
Variation modeling
TCL
Perl
Python
Timing closure

Additional Information

Minimum Education: Bachelor's degree
Required Previous Experiences: At least 3 years of relevant experience
Experience with static timing analysis, noise analysis, and fixing noise in designs
Experience with variation modeling
Experience with TCL and either Perl or Python
Preferred Qualifications: Prior experience performing timing analysis in high-speed digital designs such as CPUs
Experience with a static timing analysis tool such as PrimeTime or Tempus
Knowledge of physical design tools and methodology, including logic synthesis, PnR, parasitic extraction, and logic equivalence
Understanding of deep sub-micron technologies and scaling trends
Working knowledge of CPU microarchitecture
Data parsing, analysis, and representation or plotting skills

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