CPU Design Timing Engineer at Apple

The CPU Design Timing Engineer is responsible for CPU timing closure, including developing and scripting timing flows, collaborating with CAD, CPU micro-architecture, and implementation teams, and performing timing analysis, closure, noise analysis, variation modeling, and constraint work. The role requires a bachelor's degree and at least 10 years of relevant experience, along with experience using static timing analysis tools, multi-clock and power-domain analysis, TCL, Perl or Python, and SDC commands.