Description
The CPU Design Timing Engineer will own timing closure for a CPU project, develop and script timing flows, and collaborate with CAD, CPU micro-architecture, and implementation teams. The role requires a bachelor's degree and at least three years of relevant industry experience, along with scripting and debugging experience in TCL, Perl, or Python. Preferred qualifications include high-performance CPU implementation experience, CPU microarchitecture knowledge, physical design tool expertise, experience with GHz+ designs and multiple clock and power domains, static timing tool experience, and knowledge of cross-talk, noise, OCV, uncertainty, and derate methodologies.
