Description
The CPU Design Timing Engineer will own the timing closure of a CPU project, develop and script timing flows, and collaborate with CAD, CPU micro-architecture, and implementation teams. The role requires a minimum bachelor's degree and experience with TCL, Perl, or Python; preferred qualifications include high-performance CPU implementation experience, CPU microarchitecture knowledge, physical design tools, multi-clock and power-domain timing, static timing tools, and cross-talk, noise, OCV, uncertainty, and derate methodology.
