Description
Apple’s Silicon Engineering Group is hiring a CPU Gate Level Synthesis Engineer to assess and optimize the quality of early-stage high-performance, low-power digital CPU designs. The role runs RTL-to-gate synthesis, evaluates timing, power, and area, improves synthesis flows, integrates DFT, develops constraints, and collaborates with RTL, physical design, timing, and DFT teams. A minimum bachelor’s degree and experience in digital logic design, RTL synthesis, or physical design are required; CPU implementation experience and scripting proficiency are preferred.
