CPU Physical Design Engineer at Intel

Compensation

$105,650 – $149,150/yr

Location: Austin, Texas
Type: Full-time
Level: entry

Description

Intel is hiring a CPU Physical Design Engineer for its CPU development team in Austin, Texas. The role performs RTL-to-GDS physical design implementation for custom CPU designs, including synthesis, floorplanning, place and route, clock-tree synthesis, static timing, power and reliability analysis, verification and signoff, timing closure, and design-flow automation. The position requires a relevant bachelor's degree with at least 2 years of experience or a relevant master's degree with at least 1 year of experience, plus experience with digital synthesis, EDA tools, physical-design verification, PV convergence, and TCL scripting. The role is on-site and offers an annual US salary range of $105,650 to $149,150.

Required Skills

Physical design
Logic synthesis
Synopsys/Cadence
Power analysis
Physical verification
TCL scripting
Timing closure
Tapeout

Additional Information

Minimum Education: Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 2+ years of relevant experience, or a master's degree or higher in one of those fields with 1+ years of relevant experience.
Required Previous Experiences: At least 1 year of digital logic synthesis experience.
At least 1 year of experience using integrated-circuit EDA tools for synthesis, place and route, static timing analysis, and design closure.
At least 1 year of PV convergence experience, including static timing and power analysis.
At least 1 year of chip physical-design verification experience, including formal equivalence, electrical rules, DRC/LVS, and noise-flow checks.
At least 1 year of TCL scripting experience.
Preferred Qualifications: Master's degree in Computer Engineering, Electrical Engineering, or a related field.
Knowledge of physical-design best practices for floorplanning, routing, and clock distribution.
Completion of at least one tapeout on an advanced technology.
Knowledge of static timing, noise analysis, and reliability-verification techniques.
Experience with CPU-level timing analysis and optimization.
Experience collaborating with clocking teams and full-chip designers to balance timing, power delivery, clocking, and partitioning.