CPU Server Physical Design Timing Engineer at Qualcomm International Inc., Mexico Branch Office

Qualcomm is hiring a CPU Physical Design Timing Engineer to define, develop, and drive timing closure for Oryon CPU cores. The role involves STA setup, convergence, signoff, timing analysis and debug across PVT conditions, STA-flow optimization, timing-methodology development, automation scripting, and collaboration with microarchitecture, RTL, implementation, and central timing teams. Candidates need a bachelor's, master's, or PhD in a relevant field plus 2–4 years of related hardware, software, electrical, or systems engineering experience, along with strong STA, digital-flow, and scripting expertise.