Description
Arm is hiring a Solutions Engineering Physical IP Engineer to develop transistor-level physical layouts for Arm custom standard cells in sub-3nm process nodes. The role involves interpreting schematics, creating stick diagrams, optimizing placement and routing, performing DRC and LVS, debugging physical-verification issues, applying design-rule and reliability requirements, and improving power, performance, and area. The engineer will work with circuit designers, manage layout assignments, participate in peer reviews, and support less-experienced engineers, with AI-tool proficiency required and industry-standard physical-design tools desirable or expected depending on seniority.
