Description
Google is hiring a Design for Test (DFT) Engineer Lead to provide technical leadership for DFT architecture, design, verification, automation, and methodology for application-specific integrated circuits. The role leads DFT activities through ASIC development, manages project planning and quality, supports devices to production, and provides sign-off for tapeout. It requires a bachelor's degree in a relevant engineering field or equivalent practical experience, 8 years of DFT experience, and 4 years of people management experience. Preferred qualifications include a master's degree, post-silicon debugging experience, JTAG knowledge, SoC bring-up experience, and fault modeling knowledge. The position is based in Tel Aviv or Haifa, Israel, and may require in-person interviews.
