Description
Mythic is hiring an experienced Design for Testability (DFT) engineer to lead end-to-end DFT implementation and verification for complex ASIC/SoC designs, including MBIST, IJTAG, scan, and ATPG. The role is highly cross-functional, involving collaboration with RTL, physical design, STA, and analog teams, and offers exposure to AI processor development and deep neural network-related chip architecture. The ideal candidate has 8+ years of industry experience, strong expertise in SoC-level DFT methodologies and tools such as Synopsys or Siemens/Mentor, plus scripting skills and knowledge of low-power and pre-silicon test planning.
