Design for Testing (DFT) micro architect/design Engineer at Google

Seniority in posting: Mid

Location: Bengaluru, Karnataka
Level: senior
Posted: Aug 17, 2026

Description

Google is hiring a Design for Testing (DFT) micro architect/design Engineer to define and implement DFT architecture and flows for TPU and other AI/ML hardware. The role covers DFT strategy, test design rule checks, insertion of DFT logic and IP blocks, documentation of test sequences, and delivery of production and debug patterns to post-silicon engineering. Candidates need a bachelor's degree in electrical engineering or a related field, equivalent practical experience, and at least eight years of DFT implementation and validation experience.

Required Skills

DFT architecture
High-speed I/O
Analog DFT
TDRC
DFT compression
Logic BIST
TAP controller
ASIC synthesis
Verification flow
IP integration
Fault modeling
Silicon bringup

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience
Required Previous Experiences: 8 years of DFT implementation and validation experience
Multiple DFT design, verification, specification, architecture, and insertion projects
DFT techniques, tools, ASIC synthesis, simulation, and verification
Leading DFT activities across an ASIC development flow
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
IP integration, including memories, test controllers, TAP, and multi-die SoCs
Fault modeling
SoC cycles, silicon bringup, and silicon debug