Description
This is a hardware engineering vacancy focused on synthesis, formal verification, timing constraints, Perl or TCL scripting, and low-power design flows. The role requires a bachelor's, master's, or PhD in a relevant engineering or computer science field plus 6–8 years of hardware engineering or related experience, along with expertise in Synopsys Design Compiler, Cadence RC/Genus, multi-voltage and power-aware synthesis, UPF flows, formal verification, and design-to-commercialization experience.
