Design Verification Engineer - AI Accelerators at Meta

Meta’s Reality Labs is hiring a Design Verification Engineer to develop and execute verification infrastructure for machine learning IP and core IP implementations used in augmented reality and smart devices. The role involves defining test plans and methodologies, implementing SystemVerilog/UVM test benches, driving functional and code coverage, supporting integration into larger SoC environments, and improving verification processes. Candidates need extensive SystemVerilog/UVM and C/C++ verification experience, ASIC development experience, and a relevant bachelor’s degree.