Design Verification Engineer at Altera

Altera is hiring a Design Verification Engineer to design, develop, validate, and debug software abstractions and frameworks for FPGA acceleration supporting embedded, data center, and communication clients. The role focuses on UVM-based verification environments, SystemVerilog, testbenches, drivers, monitors, scoreboards, assertions, formal verification, simulation regression, coverage, and automation using Python or Perl. It requires a bachelor's or master's degree in a relevant engineering field and at least two years of ASIC or FPGA design verification experience, with a primary location of Regus, Madhapur and a Shift 1 schedule in India.