Description
Apple is hiring a Design Verification Engineer to verify innovative, high-throughput cellular baseband modems and transceiver link controllers for its silicon products. The role focuses on creating reusable UVM verification environments, coverage-driven and directed test plans, RTL simulation bring-up through sign-off, regression maintenance, and the use of LLMs and Python-based automation to improve verification quality and productivity. Candidates need a bachelor's degree and at least 10 years of relevant industry experience, along with strong System Verilog, UVM, System C, C/C++, Python, and design verification expertise.
