Apple is hiring a Design Verification Engineer to own RNM/SystemVerilog behavioral modeling and verification of analog and RF blocks within a large SoC. The role includes self-checking models, analog and digital specification assertions, and setting up the AMS environment with analog designers. The minimum qualifications are a bachelor's degree and at least 10 years of relevant industry experience, while an MSc and seven years of experience are preferred.
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technology industryCupertino, CA
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