Description
Apple is hiring a Digital Verification Engineer in Cupertino, California and various unanticipated locations throughout the United States. The role verifies complex digital intellectual property by creating block-level specifications, verification plans, test benches, drivers, reference models, checkers, and constrained-random UVM test cases. Responsibilities include formal and UVM-based simulation, System Verilog Assertions, debugging, code coverage, tape-out readiness assessment, and collaboration with system architects and digital designers. The position requires a master’s degree or foreign equivalent in an electrical or computer engineering-related field and experience with digital hardware simulation, System Verilog, Verilog or VHDL, C, Python or Perl, CAD-based chip simulation, and finite-state-machine verification. The role is full-time at 40 hours per week, with a base-pay range of $149,987 to $194,700 per year.
