Design Verification Engineer at Apple

Department: Hardware

Compensation

$174,149 – $225,300/yr

Location: Cupertino, California
Type: Full-time
Level: not_specified
Posted: Oct 1, 2026

Description

Apple is hiring a System Verilog/UVM Verification Engineer in Cupertino, California and other unanticipated locations throughout the United States. The role designs and implements testbench environments and test cases, develops UVM-based System Verilog checkers, executes regression tests, analyzes failures, traces signals with Verdi, and collaborates with design and microarchitecture teams. It requires a master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field, along with experience in System Verilog, RTL modeling, UVM testbenches, randomized testing, computer architecture, and functional coverage. The role is 40 hours per week and offers a base-pay range of $174,149 to $225,300 per year, plus medical and dental coverage and other benefits.

Required Skills

System Verilog
UVM methodology
Verdi
Functional coverage
Randomized testing
Computer architecture

Additional Information

Minimum Education: Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field
Required Previous Experiences: Writing System Verilog/Verilog RTL code to model digital circuits and digital designs
Developing testbench code using System Verilog/Verilog and logic design principles
Debugging RTL and testbench code with System Verilog/Verilog
Developing randomized testbenches with System Verilog/Verilog
Developing UVM testbenches to verify functional correctness
Using computer architecture for SOC architecture and design
Using functional coverage metrics to verify SOC design
Translation Company Name: Apple

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