Design Verification Engineer at Apple Technology Engineering B.V. & Co. KG

Apple is hiring a Design Verification Engineer to verify next-generation cellular baseband modems and RF link controllers for its silicon. The role focuses on creating reusable UVM verification environments, coverage-driven test plans, RTL simulation bring-up, regression maintenance, and debugging, while also developing ML-driven workflows and leveraging large language models. Candidates need System Verilog and UVM knowledge, experience with System C, C/C++, Python or perl, and the ability to develop design verification methodologies and automation solutions.