Description
Arm is hiring a senior design verification engineer for the ARM Neoverse Coherent Mesh Network. The role focuses on building and maintaining verification plans, developing SystemVerilog/UVM testbenches, creating stimulus and coverage, debugging regressions, and improving verification methodology for next-generation products used in networking, storage, servers, HPC, AI, and industrial applications. The position requires extensive verification and CPU microarchitecture experience, with a strong emphasis on cache coherence, memory systems, and AMBA bus protocols, and offers a competitive salary with hybrid working arrangements.
