Design Verification Engineer at Donatech

Compensation

$66 – $76/hr

Location: Cedar Rapids, Iowa
Level: senior
Posted: Sep 28, 2026

Description

The role is a W2 employee of Donatech responsible for developing verification plans, UVM/SystemVerilog environments, reusable verification components, ASIC/FPGA/SoC verification, coverage analysis, certification artifacts, and technical reviews for airborne electronic hardware. The position requires a STEM degree and at least five years of relevant experience, along with SystemVerilog, VHDL, or Verilog, simulation tools, digital-interface, timing, and scripting experience. Preferred qualifications include UVM, DO 254, coverage, video or networking technologies, project management, and risk management.

Required Skills

UVM/SystemVerilog
Verification components
Functional coverage
Simulation
Timing analysis
Python
DO 254

Additional Information

Minimum Education: Degree in Science, Technology, Engineering, or Mathematics (STEM), or an advanced degree in a related field
Required Previous Experiences: At least 5 years of relevant experience
Experience developing testbenches and verification environments in SystemVerilog, VHDL, and/or Verilog
Hands-on experience with verification and simulation tools
Experience verifying timing behavior, device-level timing constraints, and clock domain crossings
Experience with scripting languages such as Python, Perl, Linux shell, or C/C++
Preferred Qualifications: Strong experience with UVM and constrained random verification methodology
Knowledge of DO 254 processes and verification-related design assurance activities
Familiarity with chip-level verification best practices, including functional coverage, code coverage, assertions, and LEC
Experience with video or networking technologies
Ability to manage cost, schedule, and performance for verification activities
Basic risk management experience
Translation Company Name: Donatech