Description
The Design Verification Engineer will own verification for custom video codec ASICs in the Argos IP team, managing a high-level synthesis workflow from C/C++ source through generated RTL. Responsibilities include verification strategy and signoff, C/C++ and SystemVerilog/UVM test environments, C/RTL co-simulation, formal equivalence, bug hunting, coverage closure, and mentoring junior engineers. The role requires a bachelor's degree in a relevant engineering or computer science field and 8 years of design verification experience, with SystemVerilog and UVM experience required and HLS, video processing, and EDA debugging expertise preferred.
