Description
The Design Verification Engineer will ensure the functional correctness and quality of complex IP blocks and subsystems by developing reusable SystemVerilog and UVM-based verification environments, creating coverage-driven test plans and test cases, debugging RTL and testbench failures, implementing functional coverage and assertions, and automating regression suites. The role requires a bachelor’s or master’s degree in electrical or computer engineering, at least three years of ASIC/SoC design verification experience, expertise in SystemVerilog and UVM, knowledge of industry protocols, proficiency with EDA simulation tools, and scripting ability.
